Comparison of Energy and Performance Efficiency of Recent Cache Configuration Trends and Designs

Over the past ten years cache configurations and their designs have increased in importance, energy efficiency, speed, and in other aspects as well. The goal of this paper is to discuss the energy and performance efficiency of different cache designs throughout the years. A good scale efficiency for a cache could be considered a measure of its latency and energy consumption. To optimize cache efficiency, a CPU designer should focus on the RAM type and the strategy being used to determine cache block placements. The paper will illustrate the similarities between STT-RAM, SRAM, eDRAM when considering their individual effects on energy consumption and latency. As the demand for technology grows so does the demand for energy consumption, therefore over the past ten years the use of STT-RAMs increased as they use up less energy. More designers are also pushing towards SRAM over eDRAM as even though it is more expensive, it is much faster. Keywords— Cache Levels, Non-Volatile Memory, Volatile Memory, Cache Latency, Memory Hierarchy, SRAM, STT-RAM, eDRAM, Cache Lines, Direct Mapped, full-associative, setassociative, Miss Ratio, Hit Ratio, Energy Consumption, Cache Block, associativity